Electronic circuit

ABSTRACT

An electronic circuit includes transistors having first to third terminals, the third terminal controlling the current between the first terminal and the third terminal. The electronic circuit includes: a cascode amplifier ( 10 ) including an input transistor (Q 1 ) receiving an input signal (IN) through the third terminal, and an output transistor (QO) having the first terminal connected to the second terminal of the input transistor (QI), the third terminal connected to the ground potential via a capacitor (C 1 ) and the second terminal outputting therethrough an output signal; and a control circuit ( 20 ) including a control transistor receiving a control signal through the third terminal, and a diode connected to the first and second terminals of the control transistor (QC) in series. The third terminal of the output transistor (QO) of the cascode amplifier ( 10 ) is connected to the ground potential through the control transistor (QC) and the diode (D). The electronic circuit has a reduced signal switching time.

TECHNICAL FIELD

The present invention relates to an electronic circuit, and moreparticularly, to an electronic circuit that switches the circuitperformance and signal paths by controlling the bias of a base-groundedor gate-grounded transistor of a cascode amplifier.

BACKGROUND ART

In a high-frequency circuit used in a wireless communication circuit, anelectronic circuit adapted for switching the signal paths and gaintherein is required. FIG. 10 shows a block diagram of a high-frequencytransmission/reception unit arranged in general mobile wirelessequipment. There is used an electronic circuit for switching signalpaths of a high-frequency signal in a transmission/reception antennaswitch 102 and in a transmission/reception oscillator switch 112, andalso an electronic circuit for varying the circuit property and gain isused in part of a low noise amplifier 103, an intermediate frequencyamplifier 106, a driver amplifier 110, and a transmission amplifier 111.Hereinafter, as examples of conventional electronic circuits, twohigh-frequency switches and one gain-variable amplifier will bedescribed.

FIG. 11 shows an exemplified configuration of the conventionalelectronic circuit constituting a high-frequency switch (refer to Jpn.Pat. Laid-Open Publication No. 2000-278109, FIG. 1). In this electroniccircuit, a transistor QI and a transistor QO are cascode-connected, andthe base of the transistor QI is supplied with a high-frequency inputsignal from an input terminal IN. The transistor QO has its baseconnected to a capacitor C1 for grounding the transistor with highfrequency and a control signal terminal CTL. When the transistor QO isturned on or off by a signal from the control signal terminal CTL, ahigh-frequency signal output from a signal output terminal OUT isvaried.

FIG. 13 shows an exemplified configuration of the conventionalelectronic circuit constituting a high-frequency switch (refer to Jpn.Pat. Laid-Open Publication No. 9-121119, FIG. 1). In this electroniccircuit, a transistor QI has its collector cascode-connected toemitter-connected transistors QO1 and QO2, and the base of thetransistor QI is supplied with a high-frequency input signal from aninput terminal IN. The transistors QO1 and QO2 have their basesconnected to capacitors C1 and C2 for grounding the transistors withhigh frequency and switches SW1 and SW2 for switching the on/off of thetransistors QO1 and QO2, respectively. When the switches SW1 and SW2 areswitched, signal output terminals OUT1 and OUT2 are switched.

FIG. 14 shows an exemplified configuration of the conventionalelectronic circuit constituting a gain-variable amplifier (refer to Jpn.Pat. Laid-Open Publication No. 2002-151983, FIG. 1). In this electroniccircuit, a cascode amplifier including a transistor QI1 that has itssource grounded and a transistor QO1 that has its base grounded througha capacitor C1, and a cascode amplifier including a transistor QI2 thathas its source grounded and a transistor QO2 that has its base groundedthrough a capacitor C2 are arranged in parallel, and the transistor QI2has its gate connected to the drain of the transistor QIO through acapacitor C3. The gate of the transistor QI1 is supplied with ahigh-frequency input signal from an input terminal IN. When the biasesof the transistor QO1 and transistor QO2 are controlled by a controlpower source Vc connected through resistors R1 and R3, gains of thecascode amplifiers are controlled.

The techniques as described above are common in controlling the bias ofthe base of a base-grounded or gate-grounded transistor, which isgrounded through a capacitor, of a cascode amplifier so as to switch thecircuit performance and signal paths.

In the conventional electronic circuits in which the bias of the base ofa base-grounded or gate-grounded transistor, which is grounded through acapacitor, of a cascode amplifier is controlled so as to switch thecircuit performance and signal paths, there is a raised problem that theswitching time is delayed because it takes time to charge or dischargegrounded capacitors.

For example, in an electronic circuit shown in FIG. 12 which includesthe conventional switch shown in FIG. 11 and a control circuit having atransistor QC, resistors R2 and R3, when turning on the transistor QO,the capacitor C1 is charged by a power source Vcc2 through a resistorR1. It is assumed here that the charging voltage of the capacitor C1when the switch is off is V0, the voltage between the collector andemitter when the transistor QI is turned on is VCEQI, the voltagebetween the base and emitter when the transistor QO is turned on isVBEQO, and the base current until the transistor QO is turned on issufficiently small. Time required for the switch to be turned on fromoff is equal to time required for the charging voltage VC1 of thecapacitor C1 to be charged to VCEQI+VBEQO from V0.

The charging voltage VC1 at time “t” after the control circuit isswitched is represented by the following expression 1:VC 1(t)=(V 0−Vcc 2)exp{−t/(R 1·C 1)}+Vcc 2   (1)That is, the switching time from off to on significantly depends on atime constant of the resistor R1 and capacitor C1.

FIG. 16 shows a graph indicative of the relation between the chargingvoltage VC1 and time “t” which is obtained when the R1 is 10 kO, C1 is10 pF, Vcc2 is 3.0 V, V0 is 0.2 V, VCEQI is 0.6 V, and VBEQO is 1.2 V.It is to be noted that the switching time required to get to the stateof VC1(t)>VCEQI+VBEQO is 77 ns. The switching time from off to on can bereduced by increasing the value of the resistor R2 to increase thecharging voltage V0 at the time of off. On the other hand, since theswitching time from on to off similarly depends on the time constant ofthe resistor R2 and capacitor C1, the switching time from on to off isundesirably increased.

It is an object of the present invention to provide an electroniccircuit that can reduce the delay of the switching time due to thecharging time of a grounded capacitor.

DISCLOSURE OF THE INVENTION

The present invention provides, in a first aspect thereof, an electroniccircuit including: a cascode amplifier including an input transistorhaving first to third terminals, the third terminal of the inputtransistor controlling a current between the first terminal and thesecond terminal thereof and receiving an input signal therethrough, andan output transistor having first to third terminals, the third terminalof the output transistor controlling a current between the firstterminal and the second terminal thereof, the first terminal of theoutput transistor being connected to the second terminal of the inputtransistor, the third terminal of the output transistor being connectedto a reference potential through a capacitor, the second terminal of theoutput transistor outputting an output signal therethrough; and acontrol circuit including a control transistor having first to thirdterminals, the third terminal of the control transistor controlling acurrent between the first terminal and the second terminal thereof andreceiving a control signal therethrough, and a diode connected to thefirst and second terminals of the control transistor in series, whereinthe third terminal of the output transistor of the cascode amplifier isconnected to the reference potential through the control transistor andthe diode of the control circuit.

The present invention provides, in a second aspect thereof an electroniccircuit including: a cascode amplifier including an output transistorhaving first to third terminals, the third terminal of the outputtransistor controlling a current between the first terminal and thesecond terminal and connected to a reference potential through acapacitor, the first terminal of the output transistor receiving aninput signal therethrough, the second terminal of the output transistoroutputting an output signal therethrough, and a current sourcetransistor having first to third terminals, the third terminal of thecurrent source transistor controlling a current between the firstterminal and the second terminal thereof, the current source transistordetermining an amount of the current between the first terminal and thesecond terminal of the output transistor during an on-state of theoutput transistor, the first terminal of the output transistor beingconnected to the second terminal of the current source transistor; and acontrol circuit including a control transistor having first to thirdterminals, the third terminal of the control transistor controlling acurrent between the first terminal and the second terminal thereof andreceiving a control signal therethrough, and a diode connected to thefirst and second terminals of the control transistor in series, wherein:the third terminal of the output transistor of the cascode amplifier isconnected to the reference potential through the control transistor andthe diode of the control circuit.

According to the electronic circuit of the present invention, by using acontrol circuit having a diode that is connected to first and secondterminals of a transistor in series, discharge amount of a groundedcapacitor of a cascode amplifier can be reduced when the cascodeamplifier is turned off. Consequently, recharging time can be reduced,and the switching time from off to on can be reduced without increasingthe switching time from on to off.

Especially, in switching on/off of the cascode amplifier, when the sumof a voltage drop between the first terminal and second terminal of aninput transistor and a voltage drop between the first terminal and thirdterminal of an output transistor, the sum turning off the cascodeamplifier, is equal to a voltage drop by the control circuit, theswitching circuit implemented by the electronic circuit of the presentinvention can be switched in significantly short switching time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an electronic circuit according to afirst embodiment of the present invention;

FIG. 2 is a circuit diagram of an exemplified modification of theelectronic circuit shown in FIG. 1;

FIG. 3 is a circuit diagram of an electronic circuit according to asecond embodiment of the present invention;

FIG. 4 is a circuit diagram of an exemplified modification of theelectronic circuit shown in FIG. 3;

FIG. 5 is a circuit diagram of an electronic circuit according to athird embodiment of the present invention;

FIG. 6 is a circuit diagram of an electronic circuit according to afourth embodiment of the present invention;

FIG. 7 is a circuit diagram of an electronic circuit according to afifth embodiment of the present invention;

FIG. 8 is a circuit diagram of an electronic circuit according to asixth embodiment of the present invention;

FIG. 9 is a circuit diagram of an electronic circuit according to afirst example according to the present invention;

FIG. 10 is a block diagram of a high-frequency transmission/receptionunit arranged in a general mobile wireless equipment;

FIG. 11 is a circuit diagram of a conventional electronic circuit;

FIG. 12 is a circuit diagram of another conventional electronic circuit;

FIG. 13 is a circuit diagram of another conventional electronic circuit;

FIG. 14 is a circuit diagram of another conventional electronic circuit;

FIG. 15 is a circuit diagram of another conventional electronic circuit;

FIG. 16 is a graph exemplarily indicative of the switching time of theconventional electronic circuit;

FIG. 17 is a graph exemplarily indicative of the relation between thecollector current and on-voltage;

FIG. 18 is a graph exemplarily indicative of the switching time of theconventional electronic circuit;

FIG. 19 is a graph exemplarily indicative of the switching time of theelectronic circuit of the present invention;

FIG. 20 is a graph exemplarily indicative of the switching time of theconventional electronic circuit;

FIG. 21 is a graph exemplarily indicative of the switching time of theelectronic circuit of the present invention;

FIG. 22 is a circuit diagram of an electronic circuit according to asecond example according to the present invention;

FIG. 23 is a circuit diagram of an electronic circuit according to athird example of the present invention;

FIG. 24 is a circuit diagram of an exemplified modification of theelectronic circuit of the third example;

FIG. 25 is a circuit diagram of an electronic circuit according to afourth example of the present invention;

FIG. 26 is a circuit diagram of an exemplified modification of theelectronic circuit shown in FIG. 25;

FIG. 27 is a circuit diagram of an exemplified modification of theelectronic circuit shown in FIG. 22; and

FIG. 28 is a circuit diagram of an electronic circuit according to afifth example according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The electronic circuit according to embodiments of the present inventionwill be described below with reference to the accompanying drawings.

Referring to FIG. 1 showing an electronic circuit according to a firstembodiment of the present invention, the electronic circuit includes acascode amplifier 10 that has transistors whose third terminal is usedfor controlling a current between the first terminal and secondterminal, and a control circuit. The cascode amplifier 10 has an inputtransistor QI whose third terminal receives an input signal from ahigh-frequency signal input terminal IN, and an output transistor QOwhose first terminal is connected to the second terminal of the inputtransistor QI, and whose third terminal is connected to a referencepotential through a capacitor C1, and whose second terminal outputs anoutput signal. The control circuit 20 has a control transistor QC whosethird terminal receives a control signal from a control signal terminalCTL, and a diode D that is connected to the first and second terminalsof the control transistor QC in series. In the present electroniccircuit, the output transistor QO has its third terminal connected tothe reference potential through the control circuit 20, and outputamount of an input signal to an output terminal OUT can be controlled bycontrolling the bias of the third terminal of the output transistor QO.

A power source Vcc2 and a resistor R1 configure a bias circuit thatbiases the third terminal of the output transistor QO. The presentinvention is effective so long as the bias circuit that biases the thirdterminal of the output transistor QO is not an ideal voltage sourcewhose internal impedance is zero. This is because a problem of the delaydue to the charging time of a capacitor is raised even though other biascircuits such as a current mirror or a current source are used.

In the above-described electronic circuit, in case the transistor is abipolar transistor, the first terminal is the emitter, the secondterminal is the collector, and the third terminal is the base. In casethe transistor is a field-effect transistor, the first terminal is thesource, the second terminal is the drain, and the third terminal is thegate.

The performance of the first embodiment shown in FIG. 1 will bedescribed for the case where all the transistors are bipolartransistors. In turning on the cascode amplifier 10, the capacitor C1 ischarged by the power source Vcc2 through the resistor R1. It is assumedherein that the charging voltage of the capacitor C1 when the switch isoff is V0, the voltage between the collector and emitter when the inputtransistor QI is turned on is VCEQI, the voltage between the collectorand emitter when the input transistor QI is turned off is VCEQIOFF, thevoltage between the base and emitter when the output transistor QO isturned on is VBEQO, and the base current until the output transistor QOis turned on is sufficiently small. Time required for the switch to beturned on from off is equal to time required for the charging voltageVC1 of the capacitor C1 to be charged to VCEQI+VBEQO from V0. So far,the performance is similar to the case of the conventional switch shownin FIG. 12.

FIG. 2 shows a circuit diagram of an exemplified modification of thefirst embodiment, in which the control circuit 20 shown in FIG. 1 isprovided with a resistor R2. In the modification, if the resistor R2 is0 O, the voltage between the collector and emitter when the controltransistor QC is turned on is VCEQC, and a voltage drop of the diode Dis VD, the charging voltage VC1 of the capacitor C1 when the switch isoff is VCEQC+VD. Since the charging voltage VC1 by the conventionalswitch shown in FIG. 12 is VCEQC, time required for the switch to beturned on from off is reduced when calculated using the expression 1 asdescribed before. Since the value of the resistor R2 can be reduced andthe time constant of the resistor R2 and capacitor C1 can be reduced,the switching time from on to off can be reduced.

Furthermore, in case VCEQC+VD=VCEQIOFF+VBEQO, since the charging voltageVC1 when the switch is off is the maximum voltage that can turn off theswitch, the switching time from off to on can be reduced to the minimum.The relation of VCEQC+VD≈VCEQIOFF+VBEQO can be realized easily in anintegrated circuit. The relation of VD=VBEQO can be realized by makingthe diode D from the pn junction having the layered structure same asthe base and emitter of the output transistor QO. The relation ofVCEQC=VCEQIOFF can be realized by lowering the current density when thecontrol transistor QC is turned on to the extent at which the inputtransistor QI is turned off.

FIG. 17 shows the relation between the collector current and on-voltage.As shown in FIG. 17, when biasing the collector current of the inputtransistor QI with 4.5 mA, the on-voltage VCEQI assumes 0.6 V, whereasthe off-voltage VCEQIOFF assumes 0.3 V. If the collector current densityis lowered, the on-voltage VCEQC of the control transistor QC can bemade close to VCEQIOFF. Accordingly, the relation of VCEQC=VCEQIOFF canbe realized by lowering the current density when the control transistorQC is turned on to the extent at which the input transistor QI is turnedoff, which can be realized easily by adjusting the area ratio of thetransistor.

Next, the case in which the output transistor QO is a field-effecttransistor will be described with reference to the exemplifiedmodification shown in FIG. 2. In the field-effect transistor, thevoltage value to switch the status is determined by the outputtransistor QO alone. Therefore, as for the input transistor QI and thecontrol transistor QC, the effect in case bipolar transistors are usedis equal to the effect in case field-effect transistors are used. It isassumed herein that the minimum gate voltage value of the outputtransistor QO at which the output transistor QO is turned off is VGOFF,the maximum gate voltage value of the output transistor QO at which theoutput transistor QO is turned on is VGON. The switching time from offto on can be minimized by making the voltage drop of the control circuit20 in the off state thereof close to VGOFF. So far, the performance issimilar to the case of the conventional switch shown in FIG. 15. On theother hand, since the value of the resistor R2 can be reduced by thevoltage drop of the diode D and the time constant of the resistor R2 andcapacitor C1 can be reduced, the switching time from on to off can bereduced.

Referring to FIG. 3 showing a second embodiment according to the presentinvention, the electronic circuit includes a plurality of cascodeamplifiers 10 arranged in parallel, each of which is defined in thefirst embodiment, and by connecting the third terminals of the outputtransistors QO of the plurality of cascode amplifiers 10 to thereference potential through the control circuit 20 defined in the firstembodiment, the circuit properties and gains of the cascode amplifiers10 are controlled. Since the plurality of cascode amplifiers 10 arearranged in parallel, the charging time can be reduced even though theground capacitance is increased. In this embodiment, an electroniccircuit that has two cascode amplifiers 10 arranged in parallel and hasits high-frequency output terminal OUT1 connected to a high-frequencyoutput terminal IN2 through a capacitor has a function corresponding tothat of the conventional electronic circuit shown in FIG. 15. As shownin the modification in FIG. 4, at least one of the plurality of cascodeamplifiers 10 arranged in parallel, each of which is defined in thefirst embodiment, may be controlled by the control circuit 20 defined inthe first embodiment so as to switch gain of the electronic circuit.

Referring to FIG. 5 showing an electronic circuit according to a thirdembodiment of the present invention, the electronic circuit includes aplurality of cascode amplifiers 10 (10 ₁, 10 ₂, . . . , 10 _(n))arranged in parallel, each of which is defined in the first embodiment,and the third terminals of the input transistors QI of the plurality ofcascode amplifiers 10 are supplied with a common input signal. Outputterminals to which the input signal is to be output are switcheddepending on control signals CTL₁, CTL₂, . . . , CTL_(n) delivered tothe third terminals of the control transistors QC of the controlcircuits 20 ₁, 20 ₂, . . . , 20 _(n). When at least one of the controlcircuits 20 ₁, 20 ₂, . . . , 20 _(n) is set to be the control circuitthat is defined in the first embodiment, the switching time of the pathcan be reduced.

Referring to FIG. 6 showing a fourth embodiment of the presentinvention, the configuration of the fourth embodiment is similar to thatof the third embodiment except that input transistors QI of the cascodeamplifiers 10 are made common. Similar to the third embodiment, when atleast one of the control circuits 20 ₁, 20 ₂, . . . , 20 _(n) is set tobe the control circuit that is defined in the first embodiment, theswitching time of the path can be reduced. In the fourth embodiment, thesecond terminals of the output transistors QO of the cascode amplifiers10 may be connected to each other.

Since the input transistor QI is common, when one of the paths is onwithout fail, the input transistor QI is also on. Accordingly, themaximum voltage of the control circuit 20 m that turns off an arbitrarypath “m” is VCEQI+VBEQOm, where the VCEQI is the voltage between thecollector and emitter when the input transistor QI is turned on, theVBEQOm is the voltage between the base and emitter when the transistorQOm is turned on, and the transistors are bipolar transistors.

In above-described first to fourth embodiments, the first terminals ofthe output transistors QO of the cascode amplifiers 10 are connected toeach other, and output signals from the first terminals of the outputtransistors QO can be varied depending on the control signals deliveredto the third terminals of the control transistors QC of the controlcircuits 20.

Referring to FIG. 7 showing a fifth embodiment of the present invention,the electronic circuit includes a cascode amplifier 30 that hastransistors whose third terminal is used for controlling a currentbetween the first terminal and second terminal, and a control circuit 20that is defined in the first embodiment. The cascode amplifier 30 has anoutput transistor QO whose third terminal is connected to a referencepotential through a capacitor, whose first terminal receives an inputsignal, and whose second terminal outputs an output signal, and acurrent source transistor QB that determines the amount of a currentbetween the first terminal and second terminal of the output transistorQO when the output transistor QO is on, and the output transistor QO hasits first terminal connected to the second terminal of the currentsource transistor QB. The output transistor QO has its third terminalconnected to a reference potential through the control circuit 20, andcontrols the bias of the third terminal of the output transistor QO soas to control the output amount of the input signal to an outputterminal OUT. The effect of the fifth embodiment is similar to that ofthe first embodiment.

Referring to FIG. 8 showing a sixth embodiment of the present invention,the electronic circuit includes a cascode amplifier 10 that is definedin the first embodiment, and a cascode amplifier 30 that is defined inthe fifth embodiment, which are arranged in parallel. The respectivecascode amplifiers 10 and 30 are supplied with a common input signal,and the control circuit 20 switches the signal output terminals. When atleast one of the control circuits 20 ₁ and 20 ₂ is controlled by thecontrol circuit that is defined in the first embodiment, the switchingtime of the path can be reduced.

In the electronic circuits of the above embodiments, the transistors maybe selected from the bipolar transistors or the field-effecttransistors. On the other hand, the input transistor QI and the outputtransistor QO may be a bipolar transistor and a field-effect transistor,respectively, and vice versa. A diode D of the control circuit may be ofthe pn junction whose layered structure is same as that of the base andemitter of the output transistor QO, or of the pn junction formedbetween the base and emitter of the transistor.

In above-described embodiments, circuits or components which are notrelated with the effect of the present invention, such as a matchingcircuit, a bias circuit, and a direct current blocking capacitor isomitted, on the other hand, the third terminal of the input transistoris definitely biased.

EXAMPLE

Next, specific examples of the present invention will be described. Inthe following examples, all the transistors are GaAs-HBTs (heterobipolar transistors) that are excellent in high-frequency properties,and the on-voltage between the base and emitter is set at 1.2V. On theother hand, similar effects can be obtained when using transistors ofother types such as Si bipolar transistors and SiGe-HBTs. Forsimplicity, all the reference potentials are ground, and all the powersources Vcc1 to Vcc6 are direct current voltage sources of 3.0V. All thediodes are HBTs whose bases and collectors are connected together. Thebias circuit of an emitter-grounded transistor of cascode-connectedtransistors and an input/output direct current blocking capacitors areomitted. It is to be noted that if the voltage of the referencepotentials and power sources are different, and diodes of other typessuch as those of base-emitter junction, Schottky junction, etc. areused, similar effects can be obtained.

First Example

Referring to FIG. 9 showing a first example of the present invention, abase-grounded transistor QO, whose base is grounded through a capacitorC1, is cascode-connected to the collector of an emitter-groundedtransistor QI whose base is connected to a high-frequency signal inputterminal IN. The output transistor QO has its collector connected to apower source Vcc1 through an output terminal OUT and a load Load. Theoutput transistor QO has its base biased by a power source Vcc2 througha resistor R1, and grounded through a resistor R2 and a control circuit20 having arranged therein a diode D and a control transistor QC whichhas its base connected to a control terminal CTL through a resistor R3and has its collector and emitter connected in series.

FIG. 19 shows the temporal change of the decibel ratio Gain of an outputsignal to an input signal of 2 GHz in frequency which is calculated whenthe values of resistances of the resistors R1 and R3 are 10 kO, thevalue of resistance of the resistor R2 is 0 O, and the capacitance ofthe capacitor C1 is 10 pF, and a switching signal VCTL and the chargingvoltage VC1 of the capacitor C1. When the switching time is defined as atime period after which the gain fluctuates within ±1 dB, the switchingtime is about 30 ns. FIG. 18 shows the temporal change of the Gain whichis calculated using the conventional electronic circuit shown in FIG.12, and a switching signal VCTL and the charging voltage VC1 of thecapacitor C1. The switching time is about 90 ns. According to thepresent invention, the switching time from off to on is reduced to beapproximately one third.

FIG. 20 shows the temporal change of the Gain from on to off of theconventional electronic circuit. FIG. 21 shows graphical representationsindicative of the temporal change of the gain from on to off of theelectronic circuit of the present invention. When comparing these cases,since the R2 is 0 O, the conventional electronic circuit switches fasterslightly, and there is substantially no difference.

The switching time from on to off is shorter than the switching timefrom off to on. For increasing the switching time from on to off tothereby equalize these switching times, it is sufficient to increase theresistor R2.

Second Example

FIG. 22 shows the configuration of a second example, in which thepresent invention is applied to a differential amplification circuit.Base-grounded transistors QO1 and QO2, whose bases are grounded throughcapacitors C1 and C2, respectively, are cascode-connected to thecollectors of emitter-grounded transistors QI whose bases are connectedto a high-frequency signal input terminal IN. The output transistor QO1has its collector connected to a power source Vcc1 through an outputterminal OUT1 and a load Load1. The output transistor QO2 has itscollector connected to a power source Vcc4 through an output terminalOUT2 and a load Load2. The output transistor QO1 has its base biased bya power source Vcc2 through a resistor R1, and grounded through aresistor R2 and a control circuit 20 having arranged therein a diode QD1and a control transistor QC1 which has its base connected to a controlterminal CTL1 through a resistor R3 and has its collector and emitterconnected in series. The output transistor QO2 has its base biased by apower source Vcc3 through a resistor R2, and grounded through a resistorR5 and a control circuit 20 having arranged therein a diode QD2 and acontrol transistor QC2 which has its base connected to a controlterminal CTL2 through a resistor R4 and has its collector and emitterconnected in series.

In this example, output from the input terminal IN can be switched tothe output terminals OUT1 and OUT2 by control signals from the controlterminals CTL1 and CTL2.

Similarly, the present invention can be applied to the case in whichoutput is switched to three terminals or more, as shown in FIG. 27.

Third Example

Referring to FIG. 23 shows the configuration of a third example of thepresent invention, a base-grounded transistor QO1, whose base isgrounded through a capacitor C1 is cascode-connected to the collector ofan emitter-grounded transistor QI1 whose base is connected to ahigh-frequency signal input terminal IN. Similarly, a base-groundedtransistor QO2, whose base is grounded through a capacitor C2, iscascode-connected to the collector of an emitter-grounded transistor QI2whose base is connected to the high-frequency signal input terminal IN.The output transistor QO1 has its collector connected to a power sourceVcc1 through an output terminal OUT1 and a load Load1. The outputtransistor QO2 has its collector connected to a power source Vcc4through an output terminal OUT2 and a load Load2. The output transistorQO1 has its base biased by a power source Vcc2 through a resistor R1,and grounded through a resistor R2 and a control circuit 20 havingarranged therein a diode D1 and a control transistor QC1 which has itsbase connected to a control terminal CTL1 through a resistor R3 and hasits collector and emitter connected in series. The output transistor QO2has its base biased by a power source Vcc3 through a resistor R2, andgrounded through a resistor R5 and a control circuit 20 having arrangedtherein a diode D2 and a control transistor QC2 which has its baseconnected to a control terminal CTL2 through a resistor R4 and has itscollector and emitter connected in series.

In the circuit of this example, output from the input terminal IN can beswitched to the output terminals OUT1 and OUT2 by control signals fromthe control terminals CTL1 and CTL2. Furthermore, it is possible to varythe current amount of the cascode amplifier of the transistors QI1 andQO1 as well as the cascode amplifier of the transistors QI2 and QO2 byconnecting the bases of input transistors QI1 and QI2, which receive ahigh-frequency signal, through a direct current blocking capacitor etc.,sharing the load Load1, and varying the bias amount of the inputtransistors QI1 and QI2, as shown in FIG. 24.

Fourth Example

Referring to FIG. 25 showing the configuration of a fourth example ofthe present invention, base-grounded transistors QO1 and QO2, whosebases are grounded through capacitors C1 and C2, respectively, arecascode-connected to the collector of an emitter-grounded transistor QIwhose base is connected to a high-frequency signal input terminal IN.The output transistor QO2 has its collector connected to a power sourceVcc1 through an output terminal OUT and a load Load1. The outputtransistor QO2 has its base biased by a power source Vcc3 through aresistor R2. The output transistor QO1 has its collector connected to apower source Vcc4. The output transistor QO1 has its base biased by apower source Vcc2 through a resistor R1, and grounded through a resistorR2 and a control circuit 20 having arranged therein a diode D and acontrol transistor QC which has its base connected to a control terminalCTL through a resistor R3 and has its collector and emitter connected inseries.

In this example, output to the output terminal OUT can be adjusted by acontrol signal from the control terminal CTL1. Output to the outputterminal OUT can be adjusted by a control signal from the controlterminal CTL1 similarly, when an attenuator configured by a resistoretc. is arranged on one side, as shown in FIG. 26.

Fifth Example

Referring to FIG. 28 showing the configuration of a fifth example of thepresent invention, the electronic circuit of the fifth example issimilar to that of the second example except that the diode D is sharedby the switching circuits. According to this modification, similareffects can be obtained.

The numerical values described in the above embodiments can be optimizeddepending on the object of the circuit and the properties of thetransistors.

Although the present invention has been described in accordance withpreferred embodiments thereof, it should be understood that the presentinvention is not limited to the embodiments, and various modificationsor alterations can be implemented without departing from the scope andspirit of the present invention.

1. An electronic circuit comprising: a cascode amplifier including aninput transistor having first to third terminals, said third terminal ofsaid input transistor controlling a current between said first terminaland said second terminal thereof and receiving an input signaltherethrough, and an output transistor having first to third terminals,said third terminal of said output transistor controlling a currentbetween said first terminal and said second terminal thereof, said firstterminal of said output transistor being connected to said secondterminal of said input transistor, said third terminal of said outputtransistor being connected to a reference potential through a capacitor,said second terminal of said output transistor outputting an outputsignal therethrough; and a control circuit including a controltransistor having first to third terminals, said third terminal of saidcontrol transistor controlling a current between said first terminal andsaid second terminal thereof and receiving a control signaltherethrough, and a diode connected to said first and second terminalsof said control transistor in series, wherein: said third terminal ofsaid output transistor of said cascode amplifier is connected to saidreference potential through said control transistor and said diode ofsaid control circuit.
 2. The electronic circuit according to claim 1,wherein said electronic circuit comprises a plurality of said cascodeamplifiers connected in parallel, and at least one of said thirdterminals of said output transistors of said cascode amplifiers isconnected to said reference potential through said control transistorand said diode of said control circuit.
 3. The electronic circuitaccording to claim 2, wherein said third terminals of said inputtransistors of said plurality of said cascode amplifiers are suppliedwith a common input signal, and one of terminals through which saidinput signal is to be delivered is selected depending on said controlsignal delivered to said third terminal of said control transistor ofsaid control circuit.
 4. The electronic circuit according to claim 1,wherein said cascode amplifier includes a plurality of said outputtransistors, and said first terminals of said plurality of said outputtransistors are connected together.
 5. The electronic circuit accordingto claim 2, wherein said second terminals of said output transistors ofsaid cascode amplifiers are connected together, and output signals fromsaid second terminals of said output transistors are varied depending onsaid control signal delivered through said third terminal of saidcontrol transistor of said control circuit.
 6. The electronic circuitaccording to claim 1, wherein said transistors are bipolar transistors.7. The electronic circuit according to claim 1, wherein said transistorsare field-effect transistors.
 8. The electronic circuit according toclaim 1, wherein said input transistors are bipolar transistors, andsaid output transistors are field-effect transistors.
 9. The electroniccircuit according to claim 1, wherein said input transistors arefield-effect transistors, and said output transistors are bipolartransistors.
 10. The electronic circuit according to claim 6, whereinsaid diode has a pn junction having a layered structure same as that ofsaid base and emitter of said output transistor.
 11. The electroniccircuit according to claim 6, wherein said diode has a pn junction whichis common to a pn junction formed between said base and emitter of oneof said transistors.
 12. The electronic circuit according to claim 1,wherein a voltage drop of said control circuit is equal to or less thana sum of a voltage drop between said first terminal and said secondterminal of said input transistor of said cascode amplifier and avoltage drop between said first terminal and said third terminal of saidoutput transistor of said cascode amplifier, and equal to or more thansaid voltage drop between said first terminal and said second terminalof said input transistor.
 13. The electronic circuit according to claim1, wherein a current density between said first terminal and secondterminal of said control transistor is lower than a current densitybetween said first terminal and second terminal of said inputtransistor.
 14. An electronic circuit comprising: a cascode amplifierincluding an output transistor having first to third terminals, saidthird terminal of said output transistor controlling a current betweensaid first terminal and said second terminal and connected to areference potential through a capacitor, said first terminal of saidoutput transistor receiving an input signal therethrough, said secondterminal of said output transistor outputting an output signaltherethrough, and a current source transistor having first to thirdterminals, said third terminal of said current source transistorcontrolling a current between said first terminal and said secondterminal thereof, said current source transistor determining an amountof said current between said first terminal and said second terminal ofsaid output transistor during an on-state of said output transistor,said first terminal of said output transistor being connected to saidsecond terminal of said current source transistor; and a control circuitincluding a control transistor having first to third terminals, saidthird terminal of said control transistor controlling a current betweensaid first terminal and said second terminal thereof and receiving acontrol signal therethrough, and a diode connected to said first andsecond terminals of said control transistor in series, wherein: saidthird terminals of said output transistors of said cascode amplifier isconnected to said reference potential through said control transistorand said diode of said control circuit.
 15. The electronic circuitaccording to claim 14, wherein said electronic circuit comprises aplurality of said cascode amplifiers connected in parallel, and at leastone of said third terminals of said output transistors of said pluralityof said cascode amplifiers is connected to said reference potentialthrough said control transistor and said diode of said control circuit.16. An electronic circuit comprising: a first cascode amplifierincluding an input transistor having first to third terminals, saidthird terminal controlling a current between said first terminal andsaid second terminal and receiving a first input signal, and a firstoutput transistor having first to third terminals, said third terminalof said first output transistor controlling a current between said firstterminal and said second terminal thereof, said first terminal of saidfirst output transistor being connected to said second terminal of saidinput transistor, said third terminal of said first output transistorbeing connected to a reference potential through a capacitor, saidsecond terminal of said first output transistor outputting an outputsignal therethrough; a second cascode amplifier including a secondoutput transistor having first to third terminals, said third terminalof said second output transistor controlling a current between saidfirst terminal and said second terminal thereof and connected to saidreference potential through a capacitor, said first terminal of saidsecond output transistor receiving a second input signal therethrough,said second terminal of said second output transistor outputting anoutput signal therethrough, and a current source transistor having firstto third terminals, said third terminal of said current sourcetransistor controlling a current between said first terminal and saidsecond terminal thereof, said current source transistor determining anamount of said current between said first terminal and said secondterminal of said second output transistor during an on-state of saidsecond output transistor, said first terminal of said second outputtransistor being connected to said second terminal of said currentsource transistor; and a control circuit including a control transistorhaving first to third terminals, said third terminal of said controltransistor controlling a current between said first terminal and saidsecond terminal thereof and receiving a control signal therethrough, anda diode connected to said first and second terminals of said controltransistor in series, wherein: said first cascode amplifier and saidsecond cascode amplifier are connected in parallel, and at least one ofsaid third terminals of said output transistors of said first and secondcascode amplifiers is connected to said reference potential through saidcontrol transistor and said diode of said control circuit.
 17. Theelectronic circuit according to claim 14, wherein said transistors arebipolar transistors.
 18. The electronic circuit according to claim 16,wherein said transistors are bipolar transistors.